1. Field of the Invention
The invention generally relates to the testing and debugging of the operation of an event timer, and more particularly, to an on-chip system and method for monitoring and controlling the event timer's operation for validation purpose.
2. Description of the Related Art
Event timers which are used in personal computers are intended for use by the operating system software. Different kinds of applications may be controlled by event timers, e.g. the synchronization of real time digital audio and video streams, the scheduling of threads, tasks, processes etc. using a fixed rate (periodic) interrupt generation, the scheduling of run time threads, tasks, processes etc. associated with a variable rate (aperiodic) interrupt generation, and applications on multi-processor platforms using such timers as a “platform timer”.
Recently, an event timer (“multimedia timer”—MMT) has been developed which is designated to replace previous legacy timers in a personal computer (in particular the 8254 Programmable Interval Timer, the Real Time Clock, the APIC timer and the ACPI timer).
The event timer's architecture defines a set of timers that can be used by the operating system. The timers are defined such that the operating system may be able to assign specific timers to be used directly by specific applications. Each timer can be configured to cause a separate interrupt. An interrupt may be either a (sub-millisecond) periodic interrupt, which is of much finer granularity than provided by previously used timers, or aperiodic timer interrupts.
The event timer enables higher clock resolution for improving multimedia support and enables aperiodic interrupts, improving both multimedia support and overall system performance.
The timers are implemented as a single up-counter with a set of comparators. The basic timer configuration is illustrated in FIG. 1. A clock generator 1 provides a clock signal of a fixed frequency to an up-counter 2. The count result of the up-counter increases monotonically. Each timer includes a match register 3 and a comparator 4. The timer can generate an interrupt when the pre-programmed count value in match register 3 equals the count value of the free-running up-counter 2. The interrupt is forwarded to an interrupt routing logic 5 forwarding the interrupt to appropriate parts of the microprocessor. In particular, the registers associated with the timers may be mapped to memory space allowing the CPU to directly address each of the registers.
A more detailed hardware block diagram of the event timer configuration is shown in FIG. 2. The configuration comprises a single up-counter 2 with a plurality of comparators 10, 11, 12. The count value of the single up-counter 2 increases in accordance with a clock signal received from an (external) clock generator 1. The clock frequency is preferably 14.318 MHz, and the up-counter's count value has a width of 32 bit. In accordance with the recommended hardware implementation, the clock's frequency should not be below 10 MHz. As shown in FIG. 2, the minimum recommended hardware implementation comprises three individual timers including a match register 7, 8, 9 and a comparator 10, 11, 12. Each of the timers can individually generate an interrupt when the pre-set value in its match register 7, 8, 9 equals the count value of the single up-counter 2. Each of the match registers 7, 8, 9 and the comparators 10, 11, 12 should have a width of either 32 bit (minimum) or 64 bit.
In addition, some of the timers may be enabled to generate a periodic interrupt. For this purpose such timers comprise an additional period register 13 and an adder in order to increase the match register's count value periodically.
Further, the individual registers of the event timer may be connected to a data bus allowing to read or write the individual register values.
It has become very difficult to diagnose failures in, and to measure the performance of state of the art event timers. This is because modern event timers run at very high clock speed, too fast for validation software to react in real time. Moreover, visibility of event timers inner states has become increasingly limited due to the complexity of on chip architectures and due to practical constraints on the number of externally available contact pads that can be provided on a chip package.
A need therefore exists for an event timer apparatus, for a debug interface for an event timer apparatus and a method for enabling event timer designers to debug state of the art event timers and systems more easily. More specifically, there exists a need for an on-chip system, an on-chip interface and a method for validating the event timer's functionality.
It is therefore a primary object of this invention to provide an event timer apparatus, a debug interface and a method which allow an easier validation of the event timer's functionality.
Another primary object of this invention is to provide an event timer apparatus, an on-chip debug interface and a method which allows hardware validation without fulfilling real time requirements.